The present invention relates generally to power distribution in integrated circuits. More specifically, but without limitation thereto, the present invention relates to reducing the amount of metal in integrated circuits having circuit components connected to power buses by metal grids or straps.
In a conventional method for distributing power in integrated circuit chips, power and ground traces are typically routed orthogonally to concentric power and ground straps formed in metal layers of the chip. The power and ground traces use a substantial fraction of the area of the metal layer to maintain IR drops (voltage drops due to peak current flowing through the bus resistance) within a few percent of the voltage rail. The remaining area of the metal layer between the straps is left for wiring tracks for global signals such as the clock signal. A disadvantage of the conventional method is that the amount of metal used in the concentric straps results in signal routing congestion, especially toward the center of the chip where the density of signal traces is typically the highest.
The present invention advantageously addresses the problems above as well as other problems by providing a method for concentric metal density power distribution that reduces metal density and increases available area for routing clock and signal traces.
In one embodiment, the invention may be characterized as a method for concentric metal density power distribution that includes the steps of forming a plurality of concentric straps in a metal layer of an integrated circuit chip and varying a strap width of each of the plurality of concentric straps from a maximum strap width at a periphery of the integrated circuit chip to a minimum strap width toward a center of the integrated circuit chip.
In another embodiment, the invention may be characterized as a method of concentric metal density power distribution that includes the steps of partitioning an area of standard cells in an integrated circuit chip into a plurality of power regions, forming a power boundary around each of the plurality of power regions, and forming a plurality of concentric straps in a metal layer of the integrated circuit chip wherein each of the plurality of concentric straps has a strap width that varies from a maximum strap width at a periphery of each of the plurality of power regions to a minimum strap width toward a center of each of the plurality of power regions.
The features and advantages summarized above in addition to other aspects of the present invention will become more apparent from the description, presented in conjunction with the following drawings.